I have revised my RC filter because the previous oversampling didn’t perfectly divide the digital clock which is BAD for continuous tracking.
I have empirically verified that things are good now and that this is better in the SNR-sense than a simple bandpass filter.
A minor note: spotted yet another Xilinx bug—when comparing an
std_logic_vector to a constant, the number of bits has to match!
if ( ovrsmpl_count = "01001" ) then ovrsmpl_limit <= '1'; else ovrsmpl_limit <= '0'; end if;
Can’t remember if this is something new or yet another release-dependent peculiarity.